The PR1-Appliance project is maturing quickly and we feel that it’s time to share with you it’s progress.
At first, let me remind you that PR1-Appliance is a first of it’s kind, Blackfin driven Asterisk based T1/E1 PRI appliance. The schematic is distributed under a disjunctive tri-license giving you the choice of one of the three following sets of free software/open source licensing terms:
* Mozilla Public License, version 1.1 or later
* GNU General Public License, version 2.0 or later
* GNU Lesser General Public License, version 2.1 or later
The software, Astfin2 is available under GNU General Public License, version 2.0 or later.
Since, all main subsystems with the exception of the framer are almost identical to BR4 we were able to bring them up very quickly. Thanks to ADI, we were fortunate to use few pre-production units of BF537 silicon rev. 1.0.3. That eliminated problems related to silicon anomaly #05000263 limiting uClinux kernel to access only 43MB of SDRAM and anomaly #05000305 ; Additional Hysteresis on SPORT Input Pins.
Since, I had to make only few modification to uBoot and uClinux to support 600MHz/120MHz core/bus plus 128MB of SDRAM, the board was up and running within 30 mins. No more trills related to Blackfin based boards They just work and work as expected.
The PR1-Appliance is amazingly fast, 600MHz CPU makes a difference. The most significant visible improvement over BF532 based boards is on the Ethernet side. Due to high performance PHY and BF537′s option to use L1 cache with Ethernet , tftp download speed is several times faster than on bf532 based products.
At this point we already have a very fast and small development board…sweet , but I want to see Infineon chip in action
I logged in and connected to asterisk (asterisk -vvvvrc) to see if pri/zap are loaded. Well, since everything is going so smooth a little bit of optimism is expected…
Bummer! No pri commands and no zap loaded. I need to check my config files…
Well, zaptel was not loading since we had zap channels defined but not present. libpri was not loading due to dependency problem (it wasn’t compiling). I was able to quickly correct these problems and move forward. At this point I could properly read the Chip Version (FALC chip ID), but I could not initialize the sport properly. After checking the driver code I realized that we were using SPORT0 definitions for BF532/3. We need to use different DMA channels for Sport0 on BF537 so small code modification was required. Pawel offered his help and while I was looking at SD/MMC support he quickly added sport0/BF537 to wpr1.c/h. We got full E1 span up on the first boot. The box was already connected to our digital test bench and configured to derive clock (slave mode) from our “CO”.
Just few minutes later we were making calls between Aurora-Sonata, PC based Asterisk and PR1-Appliance.
Over the next few days we conducted various tests to confirm proper functionality and reliability under full load.
I will let Pawel talk about the results as he designed and managed our test procedures.
In the meantime you can review schematics for PR1-Appliance